Your output is unknown ( X ) because your jk_ff model does not allow for proper initialization of the SR Latch. ... <看更多>

You are making an assumption that might not be valid. You are assuming that forcing S high sets the latch...it's possible that S is ... ... <看更多>

Dec 8, 2020 - Design and working of SR Flip Flop with NOR Gate and NAND Gate. SR is a digital circuit and binary data of a single bit is being stored by it. ... <看更多>